Welcome to IEEE TCCA Email-Monthly, July 2002: 1. 4th Workshop on Binary Translation submitted by: David Kaeli Call for paper: www.ece.neu.edu/info/architecture/wbt2002.htm 2. HPCA9: Ninth International Symposium on High Performance Computer Architecture submitted by: Soner Onder Call for Papers: http://www.cs.arizona.edu/hpca9/ 3. IPDPS 2003: 17th Annual International Parallel and Distributed Processing Symposium Submitted by David A. Bader Call for papers: http://www.ipdps.org/ 4. PACT 2002: The Eleventh International Conference on Parallel Architectures and Compilation Techniques Call for Participation / Call for Workshop Papers: http://www.pactconf.org Submitted by Frank Mueller * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to tcca@ele.uri.edu * To subscribe to this mailing list, please sign up at http://hopper.computer.org/correspo.nsf/signup?OpenForm * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: subscribe/unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ======================================================================= 4th Workshop on Binary Translation to be held with IEEE PACT 2002 in Charlottesville, VA September 22, 2002 Call for paper: www.ece.neu.edu/info/architecture/wbt2002.htm For more info, contact: David Kaeli kaeli@ece.neu.edu -------------------------------------------------------------------------- *----------------------------------------------------------------------- * * * HPCA-9 * * * * Call for Papers * * * * Ninth International Symposium on High Performance * * Computer Architecture * * * * Anaheim, California. Feb. 8-12, 2003 * * * * http://www.cs.arizona.edu/hpca9/ * * * * * * Important Dates * * * * Paper submission deadline : July 12, 2002 * * Workshop proposals due : July 12, 2002 * * Author Notification : Oct. 1, 2002 * * Camera ready copy due : Nov. 3, 2002 * * * *----------------------------------------------------------------------- The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Authors are invited to submit full papers on all aspects of high-performance computer architecture. Topics of interest include, but are not limited to: * Processor architectures * Cache and memory architectures * Parallel computer architectures * Impact of VLSI scaling techniques * Novel architectures for emerging applications * Power-efficient architectures * High-availability architectures * High-performance I/O architectures * Embedded and reconfigurable architectures * Real-time architectures * Interconnection networks and network interfaces * Innovative hardware/software trade-offs * Simulation and performance evaluation * Benchmarking and measurements Please check the following web site for paper submission information: http://www.cs.arizona.edu/hpca9/ The submission should not exceed 6000 words. Papers that exceed the length limit or that cannot be viewed using Adobe Acrobat Reader (version 3.0 or higher) may not be reviewed. The official submission deadline is July 12, 2002 (Midnight EST, USA). An automatic extension of one week will be given without request. No further extensions will be given. Papers may be submitted for blind review at the option of the authors. Please indicate whether the paper is a student paper for best student paper nominations. Please submit proposals for workshops to the workshop chair by July 12, 2002. Important Dates Paper submission deadline : July 12, 2002 Workshop proposals due : July 12, 2002 Author Notification : Oct. 1, 2002 Camera ready copy due : Nov. 3, 2002 General Chairs Nader Bagherzadeh, Univ. of California, Irvine Laxmi N. Bhuyan, Univ. of California, Riverside Steering Committee Dharma P. Agrawal, Univ. of Cincinnati Laxmi N. Bhuyan, Univ. of California, Riverside Yale Patt, Univ. of Texas at Austin Jean-Luc Gaudiot, Univ. of California, Irvine Joel Emer, Intel David Kaeli, Northeastern Univ. Pen-Chung Yew, Univ. of Minnesota David Lilja, Univ. of Minnesota Program Chair Rajiv Gupta, Univ. of Arizona Program Committee Todd Austin, Univ. of Michigan Pradip Bose, IBM Doug Burger, Univ. of Texas at Austin Brad Calder, Univ. of California, San Diego Dan Connors, Univ. of Colorado Tom Conte, NC State Univ. Tom Conte, NC State Univ. Darren Cronquist, HP Labs Chita Das, Penn State Univ. Sandhya Dwarkadas, Univ. of Rochester Marius Evers, AMD Kanad Ghose, SUNY Binghamton Antonio Gonzalez, UPC, Barcelona James Goodman, Univ. of Wisconsin Wei-Chung Hsu, Univ. of Minnesota Yiming Hu, Univ. of Cincinnati Stephen Jenks, Univ. of California, Irvine Steve Melvin, Flowstorm Walid Najjar, Univ. of California, Riverside Soner Onder, Michigan Technological Univ. Santosh Pande, Georgia Tech Sanjay Patel, UIUC Li-Shiuan Peh, Princeton University Timothy Mark Pinkston, USC Ronny Ronen, Intel, Israel John Shen, Intel, MRL Josep Torrellas, UIUC Mateo Valero, UPC, Barcelona Jie Wu, Florida Atlantic Univ. Yuanyuan Yang, SUNY at Stony Brook Local Arrangements Chair Stephen Jenks, Univ. of California, Irvine Workshop Chair Walid Najjar, Univ. of California, Riverside Publications Chair Li-Shiuan Peh, Princeton Univ. Finance and Registration Chair Nayla Nassif, Univ. of California, Irvine Publicity Chair Soner Onder, Michigan Technological Univ. ----------------------------------------------------------------------- If you have any questions about HPCA-9, please do not hesitate to contact me at soner@mtu.edu. Please pass this information to other people who may be interested. Thanks, Soner Onder Assistant professor Michigan Technological University ----------------------------------------------------------------------- ----------------------------------------------------------------------- 17th Annual International Parallel and Distributed Processing Symposium IPDPS 2003 http://www.ipdps.org/ DATES: April 22-26, 2003 LOCATION: Nice, France General Co-Chairs: Michel Cosnard, , and Allan Gottlieb, Program Chair: Jack Dongarra General Contact: David A. Bader In 2003, IPDPS will follow its accustomed format, providing a forum for engineers and scientists from around the world to present their latest research findings in the fields of parallel processing and distributed computing. Sponsored by the IEEE Computer Society Technical Committee on Parallel Processing, in cooperation with ACM SIGARCH, IEEE Computer Society Technical Committee on Computer Architecture, and IEEE Computer Society Technical Committee on Distributed Processing, and hosted by INRIA Sophia Antipolis, CNRS & University of Nice. ------------------------------------------------------------------------ ************************************************************************* IPDPS 2003 International Parallel and Distributed Processing Symposium http://www.ipdps.org/ CALL FOR PAPERS Submission Deadline: October 4, 2002 ************************************************************************* For more information e-mail: info@ipdps.org 17th Annual International Parallel & Distributed Processing Symposium IPDPS 2003 Tuesday, 22 April -- Saturday, 26 April, 2003 Nice Acropolis Convention Center Nice, France =20 Sponsored by: IEEE Computer Society Technical Committee on Parallel Processing In cooperation with: ACM SIGARCH IEEE Computer Society Technical Committee on Computer Architecture (TCCA) IEEE Computer Society Technical Committee on Distributed Processing (TCDP) (Hosted by INRIA Sophia Antipolis, CNRS & University of Nice ) IPDPS 2003 CALL FOR PARTICIPATION In 2003, IPDPS will follow its accustomed format, providing a forum for engineers and scientists from around the world to present their latest research findings in the fields of parallel processing and distributed computing. Workshops and tutorials serve as the "book-end" events on the first and last days. Note that in Nice the beginning day will be Tuesday the 22nd and the final day of IPDPS will be Saturday the 26th. The three intervening days open with addresses by invited speakers and focus on the presentation of contributed papers in technical sessions organized around symposium topics of interest. Particularly hot topics are further explored via panel discussions, as well as other ad hoc meetings and discussions throughout the week. Details on local accommodations as well as travel tips will be posted on the Web before the end of the year, so you are encouraged to regularly check the IPDPS Web site at www.ipdps.org for updates. General email inquiries should be addressed to . GENERAL CO-CHAIRS Michel Cosnard, Universite' de Nice & INRIA Sophia Antipolis, France Allan Gottlieb, New York University & NEC Research Institute, GENERAL VICE CO-CHAIRS Luc Bouge', ENS Cachan & IRISA, Rennes, France Charles Weems, University of Massachusetts at Amherst, WORKSHOPS --------- Workshops are an opportunity to explore special topics, and running a workshop in association with IPDPS offers many advantages. The 18 workshops held at IPDPS 2002 are already planning for continuation in 2003 and several more have been proposed. Contact General Vice Co-Chair Charles Weems for details on workshop proposals. To obtain more information on an individual IPDPS workshop, go to the IPDPS Web site at www.ipdps.org. Each workshop has its own requirements and schedule for submissions and all are linked from the IPDPS Web site. WORKSHOPS AT IPDPS 2003 ----------------------- * Heterogeneous Computing Workshop (HCW) * Workshop on Parallel and Distributed Real-Time Systems (WPDRTS) * Workshop on High-Level Parallel Programming Models & Supportive Environments (HIPS) * Workshop on Java for Parallel and Distributed Computing (JAVAPDC) * Workshop on Parallel and Distributed Image Processing, Video Processing, and Multimedia (PDIVM) * Workshop on Advances in Parallel and Distributed Computational Models (APDCM) * Reconfigurable Architectures Workshop (RAW) * Workshop on Communication Architecture for Clusters (CAC) * NSF Next Generation Systems Program Workshop (NSFNGS) * International Workshop on High Performance Computational Biology (HiCOMB) * International Workshop on Wireless, Mobile, and Ad Hoc Networks (WMAHN) * Workshop on Fault-Tolerant Parallel and Distributed Systems (FTPDS) * Workshop on Nature Inspired Distributed Computing (NIDISC) * Workshop on Formal Methods for Parallel Programming (FMPP) * Workshop on Internet Computing and E-commerce (ICEC) * Workshop on Parallel and Distributed Scientific and Engineering Computing with Applications (PDSECA) * Workshop on Massively Parallel Processing (WMPP) * Workshop on Performance Modeling, Evaluation, and Optimization of Parallel and Distributed Systems (PMEO) * Workshop on Massively Parallel Computer Aided Surgery (MPCAS) INDUSTRIAL-TRACK/COMMERCIAL EXHIBITS ------------------------------------ Industrial track presentations are an excellent opportunity for companies to showcase new technologies and to enter into the lively discussions encouraged at IPDPS. Paired with three days of "walk-up-and-talk" exhibits, industrial researchers can promote awareness about their recent technological advances and obtain feedback from a diverse audience. Industrial sponsors are linked from the IPDPS home page, giving them several months of visibility, and papers presented become part of the IPDPS proceedings. Proposals for innovative ways to showcase vendor products or to provide sponsor benefits in lieu of exhibiting are also encouraged. Companies interested in participating should contact one of the Industrial Track Co-Chairs by October 20, 2002: Isabelle Attali or Kiran Bondalapati . TUTORIALS --------- Proposals are solicited for organizing full or half-day tutorials. Interested individuals should submit a proposal by October 20, 2002 to the Tutorials Chair Patricia Teller . Contact her for details prior to submitting your proposal. IPDPS 2003 - IMPORTANT DATES 15 June 2002 Workshop Proposals Due 4 October 2002 Manuscripts Due 20 October 2002 Tutorial Proposals Due 20 October 2002 Industrial Track Submissions Due 20 December 2002 Review Decisions Mailed 24 January 2003 Print Ready Paper Due CALL FOR PAPERS Authors are invited to submit manuscripts that demonstrate original unpublished research in all areas of parallel and distributed processing including development of experimental or commercial systems. Topics of interest include but are not limited to: 1. Parallel and distributed algorithms, including communication and synchronization protocols. 2. Applications of parallel and distributed computing, including web applications, peer-to-peer computing, grid computing and scientific applications. 3. Parallel and distributed architectures, including signal and image processors, network processors, other special purpose processors, nontraditional processor technologies, network and interconnect architecture, and performance modeling and evaluation. 4. Parallel and distributed software, including parallel programming languages and compilers, operating systems, runtime, middleware, libraries, programming environments and tools for parallel and distributed computing. BEST PAPER AWARDS ----------------- Awards will be given for the best paper in each of the four conference topics. The selected papers will also be considered for possible publication in a special issue of the Journal of Parallel and Distributed Computing. WHAT TO SUBMIT -------------- Submitted manuscripts may not exceed 12 single-spaced pages of text using 12-point size type on 8.5x11 inch pages. References, figures, tables, etc. may be included in addition to the twelve pages of text. Hardcopy submissions will be accepted, but files in either PostScript (level 2) or PDF format are strongly encouraged. (Note: Authors need to make sure that the electronically submitted files will print on a PostScript printer that uses 8.5x11 inch paper.) Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the conference attendees. Submitted papers may not have appeared in or be considered for another conference. Submission procedures are available via Web access at www.ipdps.org. For those who have only e-mail access, send an e-mail message to for an automatic reply that will contain detailed instructions for submission of manuscripts. If no electronic access is available, contact the program chair at the address given below. All manuscripts will be reviewed. Manuscripts must be received by October 4, 2002 at 12 Noon EST. (Note: Authors will be granted an automatic extension of up to 1 week (168 hours) without making a special request. However, no further extensions will be granted.) Submissions received after the due date or exceeding the length limit may not be considered. Notification of review decisions will be mailed by December 20, 2002. Camera-ready papers will be due January 24, 2003. IPDPS 2003 Proceedings for both contributed papers and workshops will be published by the IEEE Computer Society Press on CD-ROM and will be distributed at the Symposium along with a hard copy volume of abstracts. PROGRAM CHAIR Jack Dongarra University of Tennessee 1122 Volunteer Blvd Knoxville, TN 37996-3450 USA PROGRAM VICE-CHAIRS * ALGORITHMS Yves Robert, Ecole Normale Supe'rieure de Lyon * APPLICATIONS David Walker, Cardiff University * ARCHITECTURES Josep Torrellas, University of Illinois at Urbana-Champaign * SOFTWARE John Mellor-Crummey, Rice University =20 PROGRAM COMMITTEE Giovanni Aloisio, University of Lecce, Italy Eduard Ayguade, Centre Europeu de Parallelisme de Barcelona, Spain Mark Baker, University of Portsmouth, UK Laxmi Bhuyan, University of California, Riverside Henri Casanova, University of California, San Diego Serge Chaumette, University of Bordeaux, France Jong-Doek Choi, IBM Research Marcelo Cintra, University of Edinburgh, UK Simon Cox, Southampton University, UK Chita Das, Pennsylvania State University Peter Dickman, University of Glasgow, UK John Drake, Oak Ridge National Laboratory Thomas Fahringer, University of Vienna, Austria Wu-Chun Feng, Los Alamos National Laboratory Renato Figueiredo, Northwestern University Robert Fowler, Rice University Manoj Franklin, University of Maryland, College Park Guang Gao, University of Delaware Martyn Guest, Daresbury Laboratory, UK Yike Guo, Imperial College, UK John Gurd, University of Manchester, UK Mark Heinrich, Cornell University Jeffrey Hollingsworth, University of Maryland Jesu's Labarta, Technical University of Catalonia, Spain Domenico Laforenza, CNUCE-CNR Pisa, Italy Evangelos Markatos, ICS-FORTH & University of Crete, Greece Jose Moreira, IBM Research Michael O'Boyle, University of Edinburgh, Scotland D.K. Panda, Ohio State University Timothy Pinkston, University of Southern California Omer Rana, Cardiff University, UK Michael M. Resch, High Performance Computing Center, Stuttgart, Germany Wojciech Rytter, University of Liverpool, UK Yousef Saad, University of Minnesota Pascal Sainrat, Universite' Paul Sabatier, Toulouse, France Rizos Sakellariou, University of Manchester, UK Andre' Schiper, Ecole Polytechnique Fe'de'rale de Lausanne, Switzerland Jennifer Schopf, Northwestern University Bernard Schutz, MPI for Gravitational Physics, Germany Steve Scott, Cray Research Leonel Seabra de Sousa, Instituto Superior Te'cnico, Portugal Per Stenstrom, Chalmers University, Sweden Quentin F. Stout, University of Michigan Thomas Stricker, ETH Zurich, Switzerland Alan Sussman, University of Maryland Sivan Toledo, Tel-Aviv University, Israel Dean Tullsen, University of California, San Diego Mateo Valero, Universitat Polite`cnica de Catalunya, Spain Jeffrey Vetter, Lawrence Livermore National Laboratory Jennifer Welch, Texas A&M University Marianne Winslett, University of Illinois at Urbana-Champaign Sudha Yalamanchilli, Georgia Tech Tuesday, 22 April 2003 -- Saturday, 26 April 2003 17th International Parallel & Distributed Processing Symposium Join us in Nice on the French Riviera! IPDPS 2003 -- to be held in Nice, France -- will be hosted by INRIA, CNRS and the University of Nice. INRIA is the French Institute for research & development in information, communication, science and technology, and includes the Sophia-Antipolis INRIA Research Unit, which is located 20 miles from Nice and is neighbor to a major concentration of French high-tech industries and research centers. Similar to the American NSF, the CNRS sponsors research in high performance computing and networking. In this domain, the CNRS connects over 80 research groups in France, including the I3S laboratory, which operates in cooperation with the University of Nice Sophia Antipolis. Both INRIA and CNRS are vitally interested in promoting international exchange, making them ideal hosts for the 17th International Parallel & Distributed Processing Symposium. The Nice setting offers state-of-the-art meeting facilities in the Acropolis Convention Center, and there is a wide assortment of hotel accommodations within walking distance. Located between Cannes and Monte Carlo on the French Riviera, Nice provides a sidewalk cafe' and beach atmosphere to complement the technical resources available to IPDPS through the nearby Sophia-Antipolis INRIA Research Unit. Make sure your passports are up to date and keep next April open for your travel to the French Riviera. Visit the IPDPS Web site at www.ipdps.org for further information and regular updates on travel & accommodations. IPDPS 2003 ORGANIZATION GENERAL CO-CHAIRS * Michel Cosnard Universite' de Nice & INRIA Sophia Antipolis, France * Allan Gottlieb New York University & NEC Research Institute GENERAL VICE CO-CHAIRS Luc Bouge', ENS Cachan & IRISA, Rennes, France Charles Weems, University of Massachusetts at Amherst PROGRAM CHAIR Jack Dongarra, University of Tennessee STEERING CO-CHAIRS Viktor K. Prasanna, University of Southern California George Westrom, Future Scientists & Engineers of America TUTORIALS CHAIR Patricia J. Teller, University of Texas at El Paso INDUSTRIAL TRACK CO-CHAIRS Isabelle Attali, INRIA Sophia Antipolis, France Kiran Bondalapati, Advanced Micro Devices, Inc. PROCEEDINGS CHAIR Jose Nelson Amaral, University of Alberta, Canada FINANCE CHAIR Bill Pitts, Toshiba America Information Systems, Inc. LOCAL ARRANGEMENTS CO-CHAIRS Susamma Barua, California State University, Fullerton Francoise Baude, Universite' de Nice Sophia Antipolis, France Marie-He'le`ne Zeitoun, INRIA Sophia Antipolis, France =20 PRODUCTION CHAIR Sally Jelinek, Electronic Design Associates, Inc. PUBLICITY CO-CHAIRS David A. Bader, University of New Mexico Serge Chaumette, Universite' de Bordeaux, France =20 PUBLICITY COORDINATORS * Asia/Far East Satoshi Sekiguchi National Institute of Advanced Industrial Science & Technology, Japan * Australia/New Zealand Albert Zomaya University of Sydney * Central/South America Ricardo Correa Universidade Brazil * Europe/Africa Thomas Ludwig University of Heidelberg * Middle East Skevos Evripidou University of Cyprus STEERING COMMITTEE K. Mani Chandy, California Institute of Technology Ali R. Hurson, Pennsylvania State University Joseph JaJa,University of Maryland F. Tom Leighton, MIT Jose' Rolim, University of Geneva Sartaj Sahni, University of Florida Behrooz Shirazi, University of Texas at Arlington H.J. Siegel, Colorado State University Hal Sudborough, University of Texas at Dallas Steering Committee 2003 membership also includes the general = co-chairs, program chairs, and vice general co-chairs from 2002, 2003, & 2004. ADVISORY COMMITTEE Said Bettayeb, University of South Alabama (USA) Michael J. Flynn, Stanford University (USA) Friedhelm Meyer auf der Heide, University of Paderborn (Germany) Louis O. Hertzberger, University of Amsterdam (The Netherlands) Richard Karp, University of California, Berkeley (USA) Jan van Leeuwen, University of Utrecht (The Netherlands) David R. Martinez, MIT Lincoln Laboratory (USA) Kurt Mehlhorn, Max Planck Institute (Germany) Gary Miller, Carnegie Mellon University (USA) Juerg Nievergelt, ETH Zurich (Switzerland) Charles L. Seitz, Myricom, Inc. (USA) Ioannis Tollis, University of Texas, Dallas (USA) Leslie Valiant, Harvard University (USA) Paolo Zanella, E.B.I., Cambridge (UK) --- IPDPS 2003 - IMPORTANT DATES 15 June 2002 Workshop Proposals Due 4 October 2002 Manuscripts Due 20 October 2002 Tutorial Proposals Due 20 October 2002 Industrial Track Submissions Due 20 December 2002 Review Decisions Mailed 24 January 2003 Print Ready Paper Due David A. Bader Office: 505-277-6724 Assistant Professor and Regents' Lecturer FAX: 505-277-1439 Electrical and Computer Engineering Department University of New Mexico dbader@eece.unm.edu Albuquerque, NM 87131 http://www.eece.unm.edu/~dbader ------------------------------------------------------------------------ ============================================================================= Call for Participation / Call for Workshop Papers PACT 2002 The Eleventh International Conference on Parallel Architectures and Compilation Techniques Charlottesville, Virginia, September 22-25, 2002 http://www.pactconf.org/ sponsored by IEEE TCCA, IEEE TCPP, ACM SIGARCH and IFIP WG 10.3 (pending) ============================================================================= WORKSHOPS on Sep 22, 2002: . COLP 02: Workshop on Compilers and Operating Systems for Low Power submission deadline: Aug 5, 2002 http://www.ece.lsu.edu/jxr/colp02_cfp.html . Medea 2002: Workshop On Chip Multiprocessor: Processor Architecture and Memory Hierarchy Related Issue submission deadline: Jul 3, 2002 http://garga.iet.unipi.it/medea/ . SPDSEA'02: Workshop on Hardware/Software Support for Parallel and Distributed Scientific and Engineering Application (please visit www.pactconf.org for upcoming information) . WBT-2002: 4th Workshop on Binary Translation submission deadline: Jul 13, 2002 http://www.ece.neu.edu/info/architecture/wbt2002.htm TUTORIALS: . Parallel Programming with OpenMP, Rudi Eigenmann, Purdue "OpenMP is an Application Programming Interface for directive-driven parallel programming of shared memory computers. Fortran, C and C++ compilers supporting OpenMP are available for Unix and Windows workstations. Most vendors of shared memory computers are committed to OpenMP making it the de facto standard for writing portable, shared memory, parallel programs. This tutorial will provide an introduction to OpenMP. It will start with basic concepts to bring the novice up to speed. It will then present several advanced examples to give insight into the issues that come up for experienced OpenMP programmers." . Open Research Compiler (ORC): Beyond Version 1.0, Roy Ju, Intel "The objective of the Open Research Compiler (ORC) project is to provide a leading open source compiler infrastructure for the Itanium(tm) Processor Family (IA-64) to the compiler and architecture research community. Version 1.0 of ORC has been released to the open source community (http://ipf-orc.sourceforge.net/) in January, 2002. There have been hundreds of downloads, and ORC has been used as a compiler infrastructure in various university research and teaching projects. Subsequent to the Jan release, the ORC team has made a great stride on its performance by adding many optimizations and enhancements, in particular the inter-procedural analysis and function inlining enabled. These improvements are planned to be released around the mid-year of 2002 as Version 1.1. We have also got much feedback from the early users who started their research work on ORC." This tutorial will cover: - Overview of the ORC infrastructure - Features and state of ORC 1.1 - Research activities from ORC users and support in the ORC community CALL FOR PARTICIPATION PACT'02: PACT brings together researchers from architecture, compilers, languages and applications to present ground-breaking research and debate key issues of common interest. This year we have yet another exciting program, including a diverse range of workshops and tutorials that precede the main conference, a variety of keynote presentations, and a work-in-progress session. Please join us this year in historic Charlottesville, Virginia, home of the University of Virginia, which was founded by Thomas Jefferson as one of the first public universities in the United States. Charlottesville is nestled next to the beautiful Shenandoah mountains, with the homes of three presidents (Jefferson, Madison, and Monroe), Civil War sites, and many fine wineries nearby. Student participation is especially encouraged. Some support for student travel is expected, with a special grant from IFIP to support students from developing countries. Please contact the student advocate, Steve Carr (carr@mtu.edu) for more information. Preference will be given to those students making presentations. KEYNOTES Dr. Dileep Bhandarkar, Intel, "Parallelism in Mainstream Enterprise Platforms of the Future" Dr. Steve Hammond, National Renewable Energy Laboratory, "The Role of Computational Science in Energy Efficiency and Renewable Energy" Dr. Rich Wolski, University of California, Santa Barbara, "The Computational Grid: Aggregating Performance and Enhanced Capability from Federated Resources" SESSIONS . Data Parallelism and Threading . Compiler Support for Architecture . Program Characterization . Power . Prediction . Memory Performance . Memory Aliasing . Java and IA-64 . Clustered Microarchitectures . and a Work-in-Progress session to be held in the historic U.Va. Dome Room (see the web site for submission information) PAPERS . Data-Parallel Compiler Optimizations, Daniel Chavarria-Miranda and John Mellor-Crummey - Rice University . Increasing and Detecting Memory Address Congruence Samuel Larsen, Emmett Witchell, Saman Amarasinghe - Massachusetts Institute of Technology . Transparent Threads: Resource Allocation in SMT Processors for High Single-Thread Performance Gautham Thambidorai and Donald Yeung - University of Maryland . Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures Jaewook Shin, Jacqueline Chame, and Mary W. Hall - ISI, University of Southern California . Effective Compilation Support for Variable Instruction Set Architecture Jack Liu, Tim Kong, and Fred Chow - Cgnigine . A Framework for Parallelizing Load/Stores on Embedded Processors Santosh Pande, Xiaotong Zhuang, and John S. Greenland, Jr. - Georgia Institute of Technology . Workload Design: Selecting Representative Program-Input Pairs Lieven Eeckhout, Hans Vandierendonck, and Koen De Bosschere - ELIS-Ghent University . Dataflow Frequency Analysis based on Whole Program Paths Bernhard Scholz and Eduard Mehofer - University of Vienna, Austria . Quantifying Instruction Criticality Eric S. Tune, Dean M. Tullsen, and Brad Calder - Univeristy of California San Diego . Application Transformations for Energy and Performance-Aware Device Management Taliver Heath, Eduardo Pinheiro, Jerry Hom, Ulrich Kremer, and Ricardo Bianchini - Rutgers University . Leakage Energy Management in Cache Hierarchies Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin, and Anand Sivasubramaniam - Penn State University . Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, and Michael L. Scott - University of Rochester . The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors Manuel E. Acacio, Jose Gonzalez, Jose M. Garcia and Jose Duato - University of Murcia, Spain . Predicting Conditional Branches With Fusion-Based Hybrid Predictors Gabriel Loh and Dana S. Henry - Yale University . Speculative Sequential Consistency with Little Custom Storage Chris Gniady and Babak Falsafi - Carnegie Mellon University . Cost-Effective Compiler Directed Memory Prefetching and Bypassing Daniel Ortega, Eduard Ayguade, Jean-Loup Baer, and Mateo Valero - UPC . Using the Compiler to Improve Cache Replacement Decisions Zhenlin Wang, Kathryn S. McKinley, Arnold L. Rosenberg, and Charles C. Weems - University of Massachusetts . Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines Benjamin Goldberg, Emily Chapman, Chad Huneycutt, and Krishna Palem - New York University . Speculative Alias Analysis for Executable Code Manel Fernandez and Roger Espasa - UPC . Cost Effective Memory Dependence Prediction Using Speculation Levels and Color Sets Soner Onder - Michigan Technological University . Just-In-Time Java Compilation for the Itanium Processor Tatiana Shpeisman, Guei-Yuan Lueh, and Ali-Reza Adl-Tabatabai - Intel . Eliminating Exception Constraints in Java on IA-64 Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komatsu, andToshio Nakatani - IBM, Japan . Optimizing Loop Performance for Clustered VLIW Architectures Steve Carr, Yi Qian, and Philip Sweany - Michigan Technological University . Exploiting Pseudo-schedules to Guide Data Dependence GrapYale Universityh Partitioning Alex Aleta, Josep Maria Codina, and Francisco Jesus Sanchez, Antonio Gonzalez, and David Kaeli - UPC . Efficient Interconnects for Clustered Microarchitectures Joan-Manuel Parcerisa, Julio Sahuquillo, Antonio Gonzalez, and Jose Duato - UPC -------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe